1. Field of the Invention
The present invention relates to a chip scale package, and more particularly to a chip scale package, which comprises a chip type device, i.e., a transistor having two terminals on one surface and one terminal on the other surface, and a method of fabricating the chip scale package.
2. Description of the Related Art
Generally, semiconductor devices such as transistors are packaged and these packaged devices are then mounted on a printed circuit board. Structurally, this package easily connects terminals of the semiconductor device to corresponding signal patterns of the printed circuit board and serves to protect the semiconductor device from external stresses, thereby improving reliability of the package.
In order to satisfy recent trends of miniaturization of semiconductor products, the semiconductor chip packages also have been miniaturized. Therefore, a chip scale package (also, referred to as a “Chip Size Package”) has been introduced.
FIG. 1 is a schematic cross-sectional view of a conventional chip scale package. The structure of the chip scale package 10 of FIG. 1 employs a ceramic substrate 1 and is a transistor package with three terminals.
With reference to FIG. 1, three via holes, i.e., a first via hole 2a, a second via hole 2b, and a third via hole 2c, are formed on the ceramic substrate 1. The first, the second, and the third via holes 2a, 2b, and 2c are filled with a conductive material so as to electrically connect the upper surface of the substrate 1 to the lower surface of the substrate 1. Then, a first, a second, and a third upper conductive lands 3a, 3b, and 3c are formed on the upper surfaces of the first, the second, and the third via holes 2a, 2b, and 2c, respectively. A first, a second, and a third lower conductive lands 4a, 4b, and 4c are formed on the lower surfaces of the first, the second, and the third via holes 2a, 2b, and 2c, respectively. The third upper conductive land 3c is directly connected to a terminal formed on the lower surface of the transistor 5, i.e., a mounting surface of the transistor 5 on a printed circuit board, and the first and the second upper conductive lands 3a and 3b are connected to other terminals formed on the upper surface of the transistor 5 by a wire 7. A molding part 9 using a conventional resin is formed on the upper surface of the ceramic substrate 1 including the transistor 5 in order to protect the transistor 5 from the external stresses. Thereby, the manufacture of the package 10 is completed.
FIG. 2 is a cross-sectional view of a conventional chip scale package assembly, in which the chip scale package is mounted on the printed circuit board.
As shown in FIG. 2, the manufactured transistor package 10 is mounted on the printed circuit board 20 by a reflow soldering. That is, the transistor package 10 is mounted on the printed circuit board 20 by arranging the lower conductive lands 4a, 4b, and 4c of the package 10 on the corresponding signal patterns of the printed circuit board 20 and by then connecting the lower conductive lands 4a, 4b, and 4c to the signal patterns of the printed circuit board 20 with a solder 15.
As shown in FIGS. 1 and 2, since the transistor usually has terminals on each of its two opposite surfaces, these terminals must be interconnected by wires. However, these wires require a large space on the upper surface of the chip, thereby increasing the overall height of the package. Further, since at least three via holes, corresponding to the number of terminals of the transistor, must be formed on the ceramic substrate, an area as large as the total diameters of the via holes is further required. Moreover, in order not to connect the conductive lands formed on the upper and the lower surfaces of the via holes to each other, the conductive lands must be spaced from each other by a minimum interval. Therefore, the substrate has a large size so as to satisfy the aforementioned conditions, and the size of the substrate imposes a limit in miniaturizing the package.
Further, the ceramic substrate, which is employed by the above-described package, is high-priced, thereby increasing the production cost of the package. Moreover, the conventional fabrication process of the package requires a wire-bonding step and a molding step as well as a die-bonding step, thereby being very complicated.
Accordingly, a packaging technique, which can minimize the size of the package and simplify its fabricating process, has been demanded.